Fault Simulation, Automatic Test pattern generation, Fault Sensitization, Fault Propagation, Line Justification, Random Test Pattern Generation, Serial Fault Simulation, Advantages, Disadvantages, Inserting Faults, Parallel Fault Simulation, Deductive Fault Simulation, Concurrent Fault Simulation, Roth's Test-Detect Algorithm
Testability of VLSI
Course Curriculum
- Lecture 1: Introduction to VLSI Testing1 hour 26 mins
- Lecture 2: Fault Modelling1 hour 41 mins
- Lecture 3: Fault Collapsing1 hour 35 mins
- Lecture 4: Logic Simulation1 hour 30 mins
- Lecture 5: Fault Simulation1 hour 31 mins
- Lecture 6A: Testability Measures58 mins
- Lecture 6B: Introduction to Automatic Test Pattern Generation40 mins
- Lecture 07: Automatic Test Pattern Generation for Combinational Circuits1 hour 19 mins
- Lecture 08: Testing of Sequential Circuits1 hour 35 mins
- Lecture 09: Testing of Memory1 hour 49 mins
Teacher

Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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