Testability of VLSI

Types of Memories, 1. Dynamic Random Access Memory (DRAM), 2. Static Random Access Memory (SRAM), 3. Cache DRAM (CDRAM), 4.Read-Only Memories (ROMs/EPROMs/EEPROMs), Memory Organization, Memory Testing, Static faults, Dynamic Faults, Fault Models, Stuck-at faults,Transition faults,Coupling faults, Neighborhood pattern sensitive fault, Address decoder fault, March Test Notation, Inversion Coupling Faults, Idempotent Coupling Faults, Dynamic Coupling Faults,Bridging Faults,Reduced Functional Fault Modeling, Multiple Fault Models, Linkage, Fault Masking Example, Functional RAM Testing with March Tests, Neighborhood Pattern-Sensitive Faults, Optimal Write Sequences, Hamiltonian sequence, PNPSFs and ANPSFs, Eulerian sequence, Testing Neighborhoods Simultaneously, Tiling Method, Two-Group Method, Testing RAM Technology and Layout-Related Faults, Cache RAM Chip Testing, Functional ROM Chip Testing, linear feedback shift register,(LFSR) in the automatic test equipment (ATE), Electrical Parametric Testing, DC Parametric Tests, Voltage Bump Test, Leakage Test, AC Parametric Tests, Address Set-Up Time Sensitivity, Access Time Tests,Running Time Tests, Tests for Sense Amplifier Recovery Fault, Test for Write Recovery Fault.