Why Testing is Important?, Requirement of Testing, Verification vs. Testing, ASIC Design Flow, Formal Verification, Formal Equivalence Checking, Formal Property Checking, Two Types of Simulation Exhaustive and Selective, Types of Testing, Characterization (Verification), Production (Testing), Burn-in, Accelerated Life test, Incoming Inspection, Wafer sort or probe, Parametric Tests, Functional Tests, Automatic Test Equipment, Advantest Model T6682 ATE, Shmoo Plot, Test Economics, Fixed Costs (FC), Variable Costs (VC), Total Costs (TC), Average Cost, Average Product, Marginal Product, Economic Efficiency, The Law of Diminishing Returns, Increasing Returns to Scale, Benefit-Cost Analysis, The Rule of Ten, Yield, Defects versus faults, Defect per Million (DPM), System DPM, Defect Level (DL), Models to Predict DPM, Brown & Williams (IBM, 1981), Binomial distribution, Agarwal Model, Poisson distribution.
Testability of VLSI
Course Curriculum
- Lecture 1: Introduction to VLSI Testing1 hour 26 mins
- Lecture 2: Fault Modelling1 hour 41 mins
- Lecture 3: Fault Collapsing1 hour 35 mins
- Lecture 4: Logic Simulation1 hour 30 mins
- Lecture 5: Fault Simulation1 hour 31 mins
- Lecture 6A: Testability Measures58 mins
- Lecture 6B: Introduction to Automatic Test Pattern Generation40 mins
- Lecture 07: Automatic Test Pattern Generation for Combinational Circuits1 hour 19 mins
- Lecture 08: Testing of Sequential Circuits1 hour 35 mins
- Lecture 09: Testing of Memory1 hour 49 mins
Teacher

Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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