ATPG for Single-Clock Synchronous Circuits, Time-Frame Expansion Method, Assumptions, Single Synchronized Clock for all FFs, Single Stuck-at Faults in Next Stage and Output Stage Blocks, No faults internal to FFs, No Faults in Clock Path, Time-Frame Expansion with D Algorithm, Sequential Depth of FF, Solved examples, Time-Frame Expansion with 9-Valued Algorithm, Time-Frame Expansion with Muth Algorithm, Time-Frame Expansion for Cyclic Circuits, Clock Faults and Multiple-Clock Circuits, Simulation-Based Sequential Circuit ATPG, CONTEST Algorithm, Dynamic Controllability.
Testability of VLSI
Course Curriculum
- Lecture 1: Introduction to VLSI Testing1 hour 26 mins
- Lecture 2: Fault Modelling1 hour 41 mins
- Lecture 3: Fault Collapsing1 hour 35 mins
- Lecture 4: Logic Simulation1 hour 30 mins
- Lecture 5: Fault Simulation1 hour 31 mins
- Lecture 6A: Testability Measures58 mins
- Lecture 6B: Introduction to Automatic Test Pattern Generation40 mins
- Lecture 07: Automatic Test Pattern Generation for Combinational Circuits1 hour 19 mins
- Lecture 08: Testing of Sequential Circuits1 hour 35 mins
- Lecture 09: Testing of Memory1 hour 49 mins
- Lecture 10: Delay Testing1 hour 26 mins
- Lecture 11: Design for Testability1 hour 25 mins
- Lecture 12: Built-in Self-Test1 hour 28 mins
- Lecture 13: Analog and Mixed-Signal Testing1 hour 38 mins
- Lecture 14: Fault Tolerant VLSI Design1 hour 27 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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