Testability of VLSI

Lessons

1. Lecture 1: Introduction to VLSI Testing

   1 hour 26 mins

   Sanjay Vidyadharan

2. Lecture 2: Fault Modelling

   1 hour 41 mins

   Sanjay Vidyadharan

3. Lecture 3: Fault Collapsing

   1 hour 35 mins

   Sanjay Vidyadharan

4. Lecture 4: Logic Simulation

   1 hour 30 mins

   Sanjay Vidyadharan

5. Lecture 5: Fault Simulation

   1 hour 31 mins

   Sanjay Vidyadharan

6. Lecture 6A: Testability Measures

   58 mins

   Sanjay Vidyadharan

7. Lecture 6B: Introduction to Automatic Test Pattern Generation

   40 mins

   Sanjay Vidyadharan

8. Lecture 07: Automatic Test Pattern Generation for Combinational Circuits

   1 hour 19 mins

   Sanjay Vidyadharan

9. Lecture 08: Testing of Sequential Circuits

   1 hour 35 mins

   Sanjay Vidyadharan

10. Lecture 09: Testing of Memory

    1 hour 49 mins

    Sanjay Vidyadharan

11. Lecture 10: Delay Testing

    1 hour 26 mins

    Sanjay Vidyadharan

12. Lecture 11: Design for Testability

    1 hour 25 mins

    Sanjay Vidyadharan

13. Lecture 12: Built-in Self-Test

    1 hour 28 mins

    Sanjay Vidyadharan

14. Lecture 13: Analog and Mixed-Signal Testing

    1 hour 38 mins

    Sanjay Vidyadharan

15. Lecture 14: Fault Tolerant VLSI Design

    1 hour 27 mins

    Sanjay Vidyadharan