Testability of VLSI

Lecture 12: Built-in Self-Test

BIST Hierarchy, BIST Implementation, BIST Pattern Generation, ROM, Linear feedback shift register (LFSR), Binary Counters, Modified Counters, LFSR and ROM, Cellular Automaton, BIST Pattern Generation, Exhaustive Pattern Generation, Hardware partitioning, Sensitized path segmentation, Pseudo-Exhaustive Pattern Generation, Random-pattern testing and fault coverages, Linear-feedback shift-register (LFSR), Pseudo-Random Pattern Generation, BIST Response Compaction, Compaction, Compression, Signature, Single Bit signature register (MISR), BILBO, BILBO in serial scan mode, BILBO in LFSR mode, BILBO in normal D flip-flop mode, BILBO in MISR mode, Test Point Insertion, Memory BIST, Concurrent BIST, Non-Concurrent BIST, Transparent Testing, mutual comparator, March Test SRAM BIST

Lesson Intro Video

Lecture 11: Design for Testability (Prev Lesson)
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