Testability of VLSI

Lecture 14: Fault Tolerant VLSI Design

Error Detection,Physical Redundancy, Dual Modular redundancy (DMR) with a comparator, Triple modular redundancy (TMR), Temporal Redundancy, Information Redundancy, Hamming Code, Odd or Even Parity Check, Information Redundancy, Error Detection in Microprocessor Cores, arithmetic codes, Re-execution with Shifted Operands (RESO) : Adder, Multipliers Tightly Lockstepped Redundant Cores, Redundant Multithreading Without Lockstepping, Dynamic Verifcation of Invariants, Control Logic Checking, Data Flow Checking, Watchdog Processors, Using Software to Detect Hardware Errors, Error Detection in Caches and Memory, Detecting Errors in Addressing, Self-Repair, MULTIPROCESSORS, Core Replacement : Faulty Cores replaced with redundant core, Using scheduler to hide faulty functional units, Sharing resources across cores, Fault Tolerant Adders, Two pair rail checker, Fault Tolerant Adders with Reversible Gates.

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Lecture 13: Analog and Mixed-Signal Testing (Prev Lesson)
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