Testability of VLSI

Delay Fault, Path-Delay Test, Path-delay fault, Non-robust path-delay test, Robust path-delay test, Delay Algebra, Five-valued algebra for path-delay tests, Test Generation for Combinational Circuits, Transition Faults, Delay Test Methodologies, Slow-Clock Combinational Test, Enhanced-Scan Test, Normal-Scan Sequential Test, Variable-Clock /Slow Clock Non-Scan Sequential Test, Rated-Clock Non-Scan Sequential Test.