Featured VLSI Architecture VLSI 19 Lessons 12 hours 37 mins Free Lessons Lecture 1: Introduction to VLSI Architecture 55 mins Sanjay Vidyadharan Lab 1: Implementation of Majority Circuit in Xilinx ISE 26 mins Sanjay Vidyadharan Lecture 2: Microprocessor Architecture 54 mins Sanjay Vidyadharan Lab 2: Implementation of Adders in Xilinx ISE Verilog Data Flow Level Modeling 20 mins Sanjay Vidyadharan Lecture 3: Computer Arithmetic Algorithms and Implementations 53 mins Sanjay Vidyadharan Lab 3: Initialization in Verilog using XILINX ISE E 17 mins Sanjay Vidyadharan Lecture 4: Instruction Set Architecture and MIPS Instructions 1 hour 8 mins Sanjay Vidyadharan Lab 4: Handling multi-bit data and Concatenation in Verilog 24 mins Sanjay Vidyadharan Lecture 5: ALU Design and Microprocessor Design 46 mins Sanjay Vidyadharan Lab 5: Decoder and Full Adder Design using Verilog in Xilinx 14 mins Sanjay Vidyadharan Lecture 6: Hardware Flow Chart Part-1 1 hour 8 mins Sanjay Vidyadharan Lab 6: Multiplexer Design using Verilog in Xilinx 16 mins Sanjay Vidyadharan Lecture 7: Hardware Flow Chart-Part-2 53 mins Sanjay Vidyadharan Lab 7: Applications of Decoder, Encoder, and Multiplexer in Xilinx Verilog 24 mins Sanjay Vidyadharan Lecture 8: Hardware Flowcharts Part-3 47 mins Sanjay Vidyadharan Lab 8: Sequential Circuit Design using Flip-flops in Xilinx 16 mins Sanjay Vidyadharan Lecture 9: Flowcharts to Datapath Control Design 44 mins Sanjay Vidyadharan Lecture 10: Timing Signals 51 mins Sanjay Vidyadharan Lecture 11: Pipelined Architecture 1 hour 1 min Sanjay Vidyadharan
Lab 2: Implementation of Adders in Xilinx ISE Verilog Data Flow Level Modeling 20 mins Sanjay Vidyadharan
Lab 7: Applications of Decoder, Encoder, and Multiplexer in Xilinx Verilog 24 mins Sanjay Vidyadharan
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