Testability of VLSI

ATPG for Single-Clock Synchronous Circuits, Time-Frame Expansion Method, Assumptions, Single Synchronized Clock for all FFs, Single Stuck-at Faults in Next Stage and Output Stage Blocks, No faults internal to FFs, No Faults in Clock Path, Time-Frame Expansion with D Algorithm, Sequential Depth of FF, Solved examples, Time-Frame Expansion with 9-Valued Algorithm, Time-Frame Expansion with Muth Algorithm, Time-Frame Expansion for Cyclic Circuits, Clock Faults and Multiple-Clock Circuits, Simulation-Based Sequential Circuit ATPG, CONTEST Algorithm, Dynamic Controllability.