Advanced VLSI Design

Lecture 3: Dynamic Registers

Limitations of Static latch and Static Flip-flops, Principle of Operation of Dynamic Registers, Dynamic Positive edge-triggered register, Clock-Skew Insensitive C2MOS Register, Dual-edge Registers, True Single-Phase Clocked Register (TSPCR), Positive Edge-Triggered Register TSPC, Pulse Register, Sense amplifier Register.

Lesson Intro Video

Demonstration 2: Latch and Flip-flops (Prev Lesson)
(Next Lesson) Lecture 4A: Pipelined Registers
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Course Curriculum

Sanjay Vidyadharan
Role : Professor
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