Advanced VLSI Design

Lecture 6: Latch Based Clocking & Asynchronous Clocking

Pipelining, Latch Based Clocking, Slack Transfer, Self-Timed Circuit Design, Completion-Signal Generation, Dual-Rail Coding, Manchester-Carry Adder Circuit, Self-Timed Adder Circuit, Replica Delay, Completion-Signal Generation using Current Sensing, Self-Timed Signaling, two-phase hand-shaking, Muller C-element, Two-Phase Self-Timed FIFO, four-phase hand-shaking, Four-Phase Self-Timed FIFO.

Lesson Intro Video

Lecture 5B : Clock Generation and Distribution Part-2 (Prev Lesson)
(Next Lesson) Lecture 7A: Interfacing Circuits – Part-1, Synchronizer, and Arbiters
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Course Curriculum

Sanjay Vidyadharan
Role : Professor
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