Advanced VLSI Design

Lecture 5 Static Timing Analysis ( 2023-24)

Timing Constraints of a Flip-flop, Setup Time, Hold Time, Clock Skew and Jitter, Clock Uncertainty, Data setup violation caused by clock uncertainty, Data hold time violation caused by uncertainty, Sources of skew, Wire mismatch (Clock interconnect length), Differences in input capacitance on the clock, varying number of Buffers input interconnect length, Positive skew: if the capture clock comes late than the launch clock, Negative skew: : if the capture clock comes early than the launch clock, Max delay violations, Min delay violations, Setup (Max) Constraint, Hold (Min) Constraint, Hold Slack, Setup Slack, Positive Slack : No Timing Violation, Negative Slack : Timing Violation, Maximum Clock Frequency, On-chip variations, OCV, Common Path & Clock Re convergence Pessimism Removal, CPPR Adjustment 0.4, Timing ARCS, Contamination Delay, Propagation Delay, Unateness of ARCS, Positive unate, Negative unate, Non-unate, Path Based Delay STA, Graph Based Delay STA, Advanced On-Chip Variation AOCV STA, Limitations of AOCV, Parametric On chip Variation POCV.

Lesson Intro Video

Lecture 4B: Static Timing Analysis 2022-S1 (Prev Lesson)
(Next Lesson) Lecture 5B: Clock Generation and Distribution Part-1
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Sanjay Vidyadharan
Role : Professor
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