Examples of Pipelined Architectures, Pipelining with Latches, Clock-Skew Insensitive C2MOS Register, Pipelined Logic using C2MOS, NORA CMOS
Advanced VLSI Design
Course Curriculum
- Demonstration 1: Installation of TSMC 180 nm Technology Files in LT SPICE23 mins
- Lecture 1: Introduction to VLSI Design1 hour 2 mins
- Lecture 2: Latch and Flip-flops1 hour 20 mins
- Demonstration 2: Latch and Flip-flops13 mins
- Lecture 3: Dynamic Registers1 hour 30 mins
- Lecture 4A: Pipelined Registers50 mins
- Lecture 4B: Static Timing Analysis27 mins
- Lecture 4A: Pipelined Registers_2022-S154 mins
- Lecture 4B: Static Timing Analysis 2022-S135 mins
- Lecture 5 Static Timing Analysis ( 2023-24)1 hour 36 mins
- Lecture 5B: Clock Generation and Distribution Part-11 hour 2 mins
- Lecture 5B : Clock Generation and Distribution Part-230 mins
- Lecture 6: Latch Based Clocking & Asynchronous Clocking1 hour 23 mins
- Lecture 7A: Interfacing Circuits – Part-1, Synchronizer, and Arbiters31 mins
- Lecture 7B: Part-2, Schmitt Triggers56 mins
- Lecture 8: Interfacing Circuits – Part-3 Level Shifters and IO PADS1 hour 15 mins
- Lecture 9: Arithmetic Circuits: Part-11 hour 13 mins
- Lecture 9: Logic Families Other than CMOS1 hour 24 mins
- Lecture 9: Arithmetic Circuits: Part-1 2022-231 hour 25 mins
- Lecture 10: Arithmetic Circuits: Part-21 hour 10 mins
- Lecture 10: Advanced VLSI Design: Arithmetic Circuits: Part-2_2022-231 hour 20 mins
- Lecture 11: Memory Design1 hour 38 mins
- Lecture 12A: Low Power VLSI Design Part-1: Gate Level Optimization1 hour 2 mins
- Lecture 12B: Low Power VLSI Design Part-2: Architecture, Algorithmic, and RTL Level Optimization33 mins
- Lecture 12C: Adiabatic Logic17 mins
- Lecture 13: Interconnects1 hour 3 mins
- Lecture 14A: Deep-Submicron MOSFET operation58 mins
- Lecture 14B: CMOS Scaling18 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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