Advanced VLSI Design

Lecture 12A: Low Power VLSI Design Part-1: Gate Level Optimization

Overview of Power Consumption, dynamic power dissipation, transition activity, Low-Power Gate-Level Design, Low-Power Architecture-Level Design, Algorithmic-Level Power Reduction, RTL Techniques for Optimizing Power, Gate-Level Design – Technology Mapping, Phase Assignment, Pin Swapping, Glitching Power, Static Glitch Example, Precomputation, Clock Gating, Input Gating, Reduced-Power Shift Register.

Lesson Intro Video

Lecture 11: Memory Design (Prev Lesson)
(Next Lesson) Lecture 12B: Low Power VLSI Design Part-2: Architecture, Algorithmic, and RTL Level Optimization
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Teacher
Sanjay Vidyadharan
Role : Professor
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