Advanced VLSI Design

Lecture 12B: Low Power VLSI Design Part-2: Architecture, Algorithmic, and RTL Level Optimization

Architecture-Level Design – Parallelism, Pipelining, Retiming, Bus Segmentation, switching activity Reduction using gray code, FSM State Encoding, Bus Encoding for Reduced Power, RTL-Level Design – Datapath Reordering, RTL-Level Design – Memory Partition.

Lesson Intro Video

Lecture 12A: Low Power VLSI Design Part-1: Gate Level Optimization (Prev Lesson)
(Next Lesson) Lecture 12C: Adiabatic Logic
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Teacher
Sanjay Vidyadharan
Role : Professor
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