Advanced VLSI Design

Lecture 2: Latch and Flip-flops

Combinational vs. Sequential Circuits, Latch vs. Flip-flop, How to Write Data into a Latch?, SR Latch with NOR, SR latch with NAND, Clocked SR Latch, D latch, Mux Based Latch, Multiplexer-based NMOS latch using NMOS-only pass transistors, Race around in Latches, Timing Constraints of a Flip-flop, Setup Time, Hold Time, propagation delay of flip-flop, Master-slave positive edge-triggered register using multiplexers, Reduced load clock load static master-slave register, Clock Jitter, Two-phase non-overlapping clocks, Single Phase Global Clock Generation, Non-overlapping Clock Generation, Solving the leakage problem in Fliop=flops using multiple-threshold CMOS.

Lesson Intro Video

Lecture 1: Introduction to VLSI Design (Prev Lesson)
(Next Lesson) Demonstration 2: Latch and Flip-flops
Back to Advanced VLSI Design

No Comments

Give a comment

Sanjay Vidyadharan
Role : Professor
Read More