Advanced VLSI Design

Timing Constraints of a Flip-flop, Setup Time Hold Time, Clock skew , Clock Jitter, Clock Uncertainty , Data setup violation caused by clock jitter, Data hold time violation caused by clock jitter, Setup (Max) Constraint, Setup Slack , Positive Slack , Negative Slack , Hold (Min) Constraint, Timing Constraints of a Sequential Circuit, Maximum Clock Frequency. Solved Examples on STA.