Advanced VLSI Design

Pipelining, Latch Based Clocking, Slack Transfer, Self-Timed Circuit Design, Completion-Signal Generation, Dual-Rail Coding, Manchester-Carry Adder Circuit, Self-Timed Adder Circuit, Replica Delay, Completion-Signal Generation using Current Sensing, Self-Timed Signaling, two-phase hand-shaking, Muller C-element, Two-Phase Self-Timed FIFO, four-phase hand-shaking, Four-Phase Self-Timed FIFO.