Lesson Archives
ATPG Algorithm, Roth’s D-Algorithm (D-ALG), Goel’s PODEM algorithm, Fujiwara and Shimono’s FAN algorithm, Prime Implicants, D-Calculus and D-Algorithm (Roth), singular cover, D-frontier, Unique D-frontier, J-frontier, Primitive D-cubes of failure (PDCF), Forward implication, Backward implication, D-Drive , Advantages and disadvantages of D-Calculus and D-Algorithm (Roth) Testing, Thermal Imaging, Functional Versus Structural Testing, Logic verification of a 32-bit ripple-carry adder, ATPG, Exhaustive, Random, Deterministic ATPG, Symbolic – Boolean Difference, Solved Examples of Boolean Difference, Problems and Solutions Boolean Difference, ATPG Algebra, D algebra Single Fault, Problems and Solutions D algebra, Solved Examples of D algebra, Static Glitch Example, Redundancy Definition for […] Fault Simulation, TESTABILITY MEASURES, Setting Difficulty levels, CC-Combinational Controllability, SCOAP Controllability and Observability, Sandia Controllability/Observability Analysis Program, 1. Combinational 0-controllability, CC0(l) 2. Combinational 1-controllability, CC1(l) 3. Combinational observability, CO(l) 4. Sequential 0-controllability, SC0(l) Sequential 1-controllability, SC1(l) 6. Sequential observability, SO(l). Solved Examples of SCOAP, Problems and Solutions SCOAP. Fault Simulation, Automatic Test pattern generation, Fault Sensitization, Fault Propagation, Line Justification, Random Test Pattern Generation, Serial Fault Simulation, Advantages, Disadvantages, Inserting Faults, Parallel Fault Simulation, Deductive Fault Simulation, Concurrent Fault Simulation, Roth's Test-Detect Algorithm Timing Constraints of a Flip-flop, Setup Time, Hold Time, Clock Skew and Jitter, Clock Uncertainty, Data setup violation caused by clock uncertainty, Data hold time violation caused by uncertainty, Sources of skew, Wire mismatch (Clock interconnect length), Differences in input capacitance on the clock, varying number of Buffers input interconnect length, Positive skew: if the […] Simulation for Design Verification, True Value Simulation, Logic verification of a 32-bit ripple-carry adder, Fault simulation for test generation, Modeling Circuits for Simulation, Function or 1. Behavior Level, 2. Logic Level, 3. Switch Level, 4. Circuit Level, 5. Timing Level. Why Circuit Level Modeling Is Important, Modeling Gates for Z and X inputs, Modeling XOR/NOR […] Functional Versus Structural Testing, Single Stuck-at faults, Delay faults, Transistor faults, Fault Detection, Fault Sensitization, Fault Propagation, Fault Justification, Fault Detectability, Fault Coverage, Fault Equivalence, Equivalence Fault Collapsing, Dominance Fault Collapsing, Checkpoint Theorem, Collapse Ratio, Simulation for Design Verification, True Value Simulation, Fault simulation for test generation. Classification of Radars, Primary Radars, Modulated CW Radar, Unmodulated CW Radar, Moving Target Indicators and Pulsed Doppler Radar, MTI Block Diagram, MTI A-Scope, Two Pulse MTI Canceller, Filter Characteristics of the Delay-line Canceler, Blind Speeds, MTI Blind Speed and Unambiguous range, Delay Line Cancellers, MULTIPLE OR STAGGERED PRF, RANGE-GATED DOPPLER FILTERS Defects, Errors, and Faults, Fabrication Faults, Fault Models, Functional Versus Structural Testing, Common Structural Fault Models, Single stuck-at faults, Multiple Stuck-at faults, Transistor open and short faults, Bridging Faults, Delay faults (transition, path). Cell Aware Fault Model Why Testing is Important?, Requirement of Testing, Verification vs. Testing, ASIC Design Flow, Formal Verification, Formal Equivalence Checking, Formal Property Checking, Two Types of Simulation Exhaustive and Selective, Types of Testing, Characterization (Verification), Production (Testing), Burn-in, Accelerated Life test, Incoming Inspection, Wafer sort or probe, Parametric Tests, Functional Tests, Automatic Test Equipment, Advantest Model T6682 […]