This video demonstrates the implementation of TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder
Digital VLSI
Home Digital VLSI TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder
Course Curriculum
- Low Power Techniques for Digital VLSI Circuits45 mins
- 180 nm CMOS Inverter Characterization with LT SPICE16 mins
- Importing CMOSS 60 nm, 45 nm, 22nm, 16nm, 10 nm, and 7nm Technology Files into LT SPICE10 mins
- Importing Stanford University CNFET model into Cadence Virtuoso15 mins
- Measurement of Power and Delay Analysis of CMOS digital Circuits in Cadence.56 mins
- Importing PTM 7nm, 16 nm, 22nm CMOS Technology files Into Virtuoso CadenceĀ®10 mins
- TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder25 mins
- TSMC 180 nm NMOS Characterization Transfer Characteristics & Output Characteristics in LT Spice10 mins
- The Layout of NAND Gate in Cadence Virtuoso. DRC and LVS Check32 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
Sir, can I get this file? I am not able to add “.include tsmc”
You can download the tsmc files from my webpage under the downloads section. There was a problem with the downloads tab, which I have rectified now. You can download it now. The .include is a spice directive the tab for which is available in LT SPICE as explained in the video. Feel free to get in touch in case the issue is still not resolved. Refer to my class https://sanjayvidhyadharan.in/lessons/180-nm-cmos-inverter-characterization-with-lt-spice/