VLSI Architecture

Lecture 11: Pipelined Architecture

Pipeline Concept, Sequential execution, Pipelined execution, Why RISC is better for Pipeling, Review - Single-Cycle Processor, Basic Pipelined Processor, Role of Cache Memory, Pipeline Performance, Pipeline Hazard, Data hazard, Instruction (control) hazard and Structural hazard, Operand Forwarding, Handling data hazards in Software, Instruction Queue, and Prefetching, Branch Prediction, Dynamic Branch Prediction, Addressing Modes

Lesson Intro Video

Lecture 10: Timing Signals (Prev Lesson)
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