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Home VLSI Architecture Lecture 7: Hardware Flow Chart-Part-2

Lecture 7: Hardware Flow Chart-Part-2

53 mins

VLSI Architecture

MIN execution unit block diagram, Rules of operation, Level 2 flowcharts, Feedback on Execution Unit Design, Feedback on Controller Design, ALU Design, Address Mode Sequences, Branch Instruction, Rules for Doing Level 1 Flowcharts, Execution Sequences for Register-to-Register, Execution Sequences with a Memory Operand Reference, Execution Sequences for Special Instructions

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Lesson Intro Video

Lab 6: Multiplexer Design using Verilog in Xilinx (Prev Lesson)
(Next Lesson) Lab 7: Applications of Decoder, Encoder, and Multiplexer in Xilinx Verilog
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Course Curriculum

Teacher
Sanjay Vidyadharan
Role : Professor
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