VLSI Design

Lecture 9: CMOS Static Logic

Static CMOS, Body-Effect, DIBL, Static Two-Input NAND Gate, Transistor Sizing for a Complex Gate, Shortest Path First Sizing, Worst Path First Sizing, Chain Network Elmore Delay, Fanin considerations, Propagation Delay as a function of fanin, Progressive sizing, Input re-ordering, Logic Restructuring, Isolating fan-in from fan-out using buffer insertion.

Lesson Intro Video

Lecture 8: CMOS Inverter Transient Response (Prev Lesson)
(Next Lesson) Lecture 10: Delays in Complex CMOS Static Logic Circuits
Back to VLSI Design

No Comments

Give a comment