VLSI Design

Lecture 10: Delays in Complex CMOS Static Logic Circuits

Logical Effort, Delay in a Logic Gates, effective fanout, Intrinsic Delay , Electrical effort, Parasitic Delay, Path effective fanout, Path Logical Effort, Path Effort H = FG, Branching Effort, Logical Effort Example, Best Stage Effort, Delay of a fanout-of-4 (FO4) inverter,Stage Delay

Lesson Intro Video

Lecture 9: CMOS Static Logic (Prev Lesson)
(Next Lesson) Lecture 11: Layout of Static CMOS Circuits
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