Noise Margin, Resistive Load Inverter, VTC Curve, Load line, Ratioed Logic, MOSFET Current Equations, Calculation of VOH, VIH, Noise Margin High NMH, Noise Margin Low NML, Enhancement-Load nMOS Inverter, Depletion-Load nMOS Inverter, The CMOS Inverter, Important properties of static CMOS, The PMOS Load Line, CMOS Inverter Load Characteristic, CMOS Inverter VTC, CMOS Inverter Switching Threshold, Static Loss, Multiple VDD for Power Reduction, Multi-Vth Design.
VLSI Design
Course Curriculum
- Demonstration 1: Installation of TSMC 180 nm Technology Files in LT SPICE23 mins
- Lecture 1: Introduction to VLSI Design1 hour 2 mins
- Lecture 2: Review of MOSFET Operation1 hour 15 mins
- Lecture 3: Deep-Submicron MOSFET operation18 mins
- Lecture 4: CMOS Technology1 hour 0 mins
- Lecture 5: CMOS Scaling16 mins
- Lecture 6: CMOS Inverter Static Characteristics1 hour 28 mins
- Lecture 6: CMOS Inverter Static Characteristics_2022-S11 hour 38 mins
- Lecture 7: MOS Capacitance18 mins
- Lecture 8: CMOS Inverter Transient Response1 hour 7 mins
- Lecture 9: CMOS Static Logic1 hour 0 mins
- Lecture 10: Delays in Complex CMOS Static Logic Circuits44 mins
- Lecture 11: Layout of Static CMOS Circuits1 hour 8 mins
- Demo on Dynamic Full Adder in LT SPICE Using 180 nm TSMC Files25 mins
- Lecture 12: Dynamic Logic1 hour 0 mins
- Lecture 13: Domino Logic43 mins
- Lecture 14: Adiabatic Logic27 mins
- Lecture 15: Pass Transistor Logic1 hour 6 mins
- Lecture 16: Arithmetic Circuits: Part-11 hour 13 mins
- Lecture 16: Arithmetic Circuits: Part-1 2022-231 hour 54 mins
- Lecture 17: Arithmetic Circuits: Part-21 hour 16 mins
- Lecture 18: Memory Design1 hour 26 mins
- Lecture 19: CMOS Testing1 hour 23 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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