VLSI Design

Static CMOS, Body-Effect, DIBL, Static Two-Input NAND Gate, Transistor Sizing for a Complex Gate, Shortest Path First Sizing, Worst Path First Sizing, Chain Network Elmore Delay, Fanin considerations, Propagation Delay as a function of fanin, Progressive sizing, Input re-ordering, Logic Restructuring, Isolating fan-in from fan-out using buffer insertion.