Lesson Archives
Crystal oscillators, Phase-Locked Loops, The XOR as a phase detector, Phase-Frequency Detector, Charge Pump, VCO, Delay-Locked Loop CMOS Inverter: Delay-Time Definitions, CMOS Inverter Transient Response, CMOS Inverter: Delay-Time Calculation, Three Methods, Average Current Model, Differential Equation Model, First Order RC delay Model, Sizing of CMOS Inverter, Sizing of CMOS Chain of Inverters, Short Circuit Loss, Switching Loss, Ring Oscillator Circuit. MOSFET Junction Capacitances, MOSFET Gate Capacitances, MOSFET Overlap Capacitances, MOSFET C-V Curve Design of Clocked Sequential Circuits, Design of sequence detector (1001), Overlapping detector, Non-overlapping detector. State diagram, State table, State Equations, Circuit Implementation. 2-bit synchronous counter, Excitation Tables, Characteristic Table,State Equations, D Flip-flop implementation, JK Flip-flop implementation, T Flip-flop implementation, Design of Mod-3 Counter, Design of Asynchronous counter, 2-bit Asynchronous counter, Design of Mod-5 Asynchronous counter. Timing Constraints of a Flip-flop, Setup Time, Hold Time, Clock skew, Clock Jitter, Clock Uncertainty, Data setup violation caused by clock jitter, Data hold time violation caused by clock jitter, Max delay violations, Min delay violations, Setup (Max) Constraint, Setup Slack, Hold (Min) Constraint, Hold Slack, Solved Examples of Static Timing Analysis, Problems and Solutions […] 4-Bit Ripple Carry Adder, Pipelined 4-Bit Adder, Pipelining with Latches, Pipelined Logic using C2MOS, NORA CMOS Latch vs. Flip-flop, Race around in Latches, Master-Slave Positive and Negative edge-triggered Flip-flop, D-type positive edge-triggered with NAND gates, JK Flip-Flop, Characteristic Table, Characteristic Equation, Design of J-K Flip-flop using D flip-flop, T Flip-Flop, Design of T Flip-flop using D flip-flop, Design of T Flip-flop using J-K flip-flop, Design of T Flip-flop using Gates. Combinational vs. Sequential Circuits, Asynchronous Sequential circuits, Synchronous Sequential circuits, Latch vs. Flip-flop, SR Latch Operation, SR Latch with NOR, SR Latv with NAND, SR Latch with Enable, D Latch with Enable, D Latch with Asynchronous PRESET and CLEAR, Latch Symbols. Limitations of Static latch and Static Flip-flops, Principle of Operation of Dynamic Registers, Dynamic Positive edge-triggered register, Clock-Skew Insensitive C2MOS Register, Dual-edge Registers, True Single-Phase Clocked Register (TSPCR), Positive Edge-Triggered Register TSPC, Pulse Register, Sense amplifier Register.