VLSI Design

Limitations of Static CMOS Logic, Static vs. Dynamic Logic, Properties of Dynamic Gate, Speed of Dynamic Logic, Transition Activity, Charge Sharing Phenomenon in Dynamic Logic, Solution to Charge Redistribution, Capacitive Coupling and Backgate (or output-to-input) coupling in Dynamic Logic, Keeper PMOS, Clock-Feedthrough, monotonically rising inputs for Dynamic gates, Problems of Cascading Dynamic Gates.