Lesson Archives
Noise Margin, Resistive Load Inverter, VTC Curve, Load line, Ratioed Logic, MOSFET Current Equations, Calculation of VOH, VIH, Noise Margin High NMH, Noise Margin Low NML, Enhancement-Load nMOS Inverter, Depletion-Load nMOS Inverter, The CMOS Inverter, Important properties of static CMOS, The PMOS Load Line, CMOS Inverter Load Characteristic, CMOS Inverter VTC, CMOS Inverter Switching Threshold, […] Technology Scaling, Constant field Scaling, Constant voltage Scaling. Crystal Growth, Silicon Ingot, Czochralski crystal puller, Cleanroom, Lithography, Oxidation, Dry or wet oxidation, duration of oxidation, Diffusion, Epitaxy, Ion-implantation, Annealing, Metallization, CMOS Fabrication Sequence, Design rules, Twin-well process, Silicon On Insulator (SOI). Implementation of SR Latch, D-Latch and D Flip-flop using 180 nm TSMC CMOS devices in LT SPICE. Combinational vs. Sequential Circuits, Latch vs. Flip-flop, How to Write Data into a Latch?, SR Latch with NOR, SR latch with NAND, Clocked SR Latch, D latch, Mux Based Latch, Multiplexer-based NMOS latch using NMOS-only pass transistors, Race around in Latches, Timing Constraints of a Flip-flop, Setup Time, Hold Time, propagation delay of flip-flop, Master-slave […] Deep-submicron definition, Threshold voltage reduction VT Roll Off Drain-induced barrier lowering (DIBL), Mobility degradation due to a vertical field, Velocity saturation effects, Channel length modulation Early Voltage, Subthreshold (weak inversion) conduction, Hot-electron effects on output resistance. A practical definition of the threshold voltage VT, inversion layer, depletion layer, work function difference, surface inversion, body effect, Derivation of MOSFET Current Equation, MOSFET Current in Linear and Saturation regions, MOSFET as Switch, NMOS can pass perfect 0 but not 1, PMOS pass perfect 1 but not 0, MOSFET Body connection, LATCH in MOSFET. NMOS & PMOS Characterization SSI, MSI, LSI and VLSI, ENAIC - The First Electronic Computer, Evolution of Digital Technology, RTL, DTL, TTL, ECL, CMOS Logic Advantages and Disadvantages, Moore’s Law, ITRS Prediction of Power Consumption, Limitations of Static CMOS, Power Dissipation in CMOS Circuits, Static Loss, Short Circuit Loss, Switching Loss, Figure of Merits of a Digital Circuits, Noise […] NMOS & PMOS Characterization