Lesson Archives
Microprocessor Design, ALU Design, Half Adder, Full Adder, CMOS 28T Adder, CMOS 28T Mirror Adder, Ripple Carry Adder, Carry Look-Ahead Adder, Carry Bypass or Carry Skip Adder, Carry Ripple versus Carry Bypass, Manchester Carry Chain, Linear Carry-Select Adder, Square Root Carry-Select Adder, Adder Delays - Comparison, Serial Adder, 4 Bit-Adder Subtractor, Binary Coded Decimal Adder. The Binary Multiplication, The Array Multiplier, The Carry-Save Multiplier, Multiplier Floorplan, Transmission Gate XOR, Adder Cells in Array Multiplier, Sequential Multiplier, Booth Algorithm, Comparators, 0’s detector, 1’s detector, Equality comparator, Magnitude comparator, Shifters, The Binary Shifter, Multi-bit Shifters, The Barrel Shifter, Logarithmic Shifter, Shifter Using Mux. NMOS Switch, PMOS Switch, NMOS-Only PTL, Level-Restorer, Single Transistor Pass Gate with Low VT, Complementary PTL, Transmission Gate PTL, Resistance of Transmission Gate, Resistance of Transmission Gate, Delay in Transmission Gate Networks, Delay in Transmission Gate Networks. Pass Transistor Logic Full Adder, XOR gate, Pass Transistor Logic Full Adder in LT SPICE using 180 nm […] Microprocessor Design, ALU Design, Half Adder, Full Adder, CMOS 28T Adder, CMOS 28T Mirror Adder, Ripple Carry Adder, Carry Look-Ahead Adder, Carry Bypass or Carry Skip Adder, Carry Ripple versus Carry Bypass, Manchester Carry Chain, Linear Carry-Select Adder, Square Root Carry-Select Adder, Adder Delays - Comparison, Serial Adder, 4 Bit-Adder Subtractor, Binary Coded Decimal Adder. Adiabatic Operation, CMOS Symmetric Pass Gate Adiabatic Logic, Clock Recovery, CMOS Symmetric Pass Gate Adiabatic Logic, Adiabatic Logic in Cadence Virtuoso. Charge Sharing Phenomenon in Dynamic Logic. Cascading Dynamic Gates. Domino Logic, Cascading Domino Logic, Designing Domino Logic, Footless Domino, Dual-Rail Domino Logic, Multiple-Output Domino, Compound Domino logic, np-CMOS. Verilog Codes for 3 X 8 Decoder with Enable, 8 X 3 Encoder, and The Multiplexer. Encoder and Decoder Application, Binary to Gray Converter in Verilog code MIN execution unit block diagram, Rules of operation, Level 2 flowcharts, Feedback on Execution Unit Design, Feedback on Controller Design, ALU Design, Address Mode Sequences, Branch Instruction, Rules for Doing Level 1 Flowcharts, Execution Sequences for Register-to-Register, Execution Sequences with a Memory Operand Reference, Execution Sequences for Special Instructions Gate Level Model of Mux in Verilog, Data-flow Model of Mux in Verilog, Implementation of Full Adder using MUX. Flowchart Objectives, Inputs required for the flow chart, MIN execution unit block diagram, Rules of operation, ALU Design, Flowchart Method, Min Instruction Format, Min Instruction Set, Level 1 flowcharts, Housekeeping tasks, Operation tasks Level 2 flowcharts.