Lesson Archives
MOSFET Large Signal Equivalent, MOSFET Small Signal Equivalent, Transconductance, Output Conductance, Backgate Transconductance, High-Frequency Model, CS Amplifier Design Steps, Load-Line Analysis to find Q, Miller Capacitance, Q-point Stability, CS Amplifier with source degeneration, CS Amplifier with source degeneration and bypass capacitor, CS Amp with Current Source Supply, P-Channel CS Amplifier, CS Amplifier with Active Load. […] A practical definition of the threshold voltage VT, inversion layer, depletion layer, work function difference, surface inversion, body effect, Derivation of MOSFET Current Equation, MOSFET Current in Linear and Saturation regions, MOSFET as Switch, NMOS can pass perfect 0 but not 1, PMOS pass perfect 1 but not 0, MOSFET Body connection, LATCH in MOSFET. Pipeline Concept, Sequential execution, Pipelined execution, Why RISC is better for Pipeling, Review - Single-Cycle Processor, Basic Pipelined Processor, Role of Cache Memory, Pipeline Performance, Pipeline Hazard, Data hazard, Instruction (control) hazard and Structural hazard, Operand Forwarding, Handling data hazards in Software, Instruction Queue, and Prefetching, Branch Prediction, Dynamic Branch Prediction, Addressing Modes Instruction Set Example, Instruction Timing State, Instruction Execution with No Overlap, Instruction Execution with Overlap, Timing Signals, Ring Counter, Counter with Decoder, Johnson Counter, Four-Phase Clocks, Two-level control store (organization), Exceptions, Interrupts, internal interrupts, external interrupts, Immediate Interrupt, Deferred Interrupt MIN execution unit block diagram, MIN execution unit block diagram, Execution Sequences for Register-to-Register, implementation of PC control, T2 Control, Register Control, Control Word Format, ALU Control, State Sequencer. Verilog Code for D Latch, D Flip-flop and D Flip-flop with Reset and Verilog Code for D Flip-flop test. State Identifiers, Register to Register Operations, Execution Sequences with a Memory Operand Reference, Branch Instruction, Examples Store Magnitude of a number, Sorting a number. Technology Scaling, constant field scaling, constant voltage scaling, Interconnects scaling. MOSFET Operation, Cut-off Region, The Threshold Voltage, Linear Region- Small VDS, Linear Region as VDS is Increased, MOSFET Current in Saturation Region, MOSFET BODY CONNECTION, NMOS Double well, MOSFET LATCH, Deep-submicron MOSFET operation, Threshold voltage reduction, VT Roll Off, Drain-induced barrier lowering (DIBL), Mobility degradation due to a vertical field, Velocity saturation effects, Channel length […] Pre-fabrication Testing / Logic Verification, Corner Analysis, Design for Testability, Observability & Controllability, Stuck-At Faults, SSL Fault Detection, Multiple Stuck-Line (MSF) Faults, Test Pattern Generation, Bridging Faults, Stuck-Open Faults, Sequential Circuit Test Generation, AdHoc Design for Testability, Scan-Path Design, Static Glitch, Scan Design, Scannable Flip-flops, Built-in Self-test (BIST), Linear-feedback shift-register (LFSR), Single Bit signature register […]