Lesson Archives
Pre-fabrication Testing / Logic Verification, Corner Analysis, Design for Testability, Observability & Controllability, Stuck-At Faults, SSL Fault Detection, Multiple Stuck-Line (MSF) Faults, Test Pattern Generation, Bridging Faults, Stuck-Open Faults, Sequential Circuit Test Generation, AdHoc Design for Testability, Scan-Path Design, Static Glitch, Scan Design, Scannable Flip-flops, Built-in Self-test (BIST), Linear-feedback shift-register (LFSR), Single Bit signature register […] Wire Geometry, Pitch, Aspect ratio, Layer Stack, Choice of Metals, Wire Resistance, Sheet resistance, Contacts Resistance, Wire Capacitance, Capacitance Trends, Polysilicon, Lumped Element Models, Elmore delay model, Repeaters, Crosstalk. Adiabatic Operation, CMOS Symmetric Pass Gate Adiabatic Logic, Clock Recovery, CMOS Symmetric Pass Gate Adiabatic Logic, Adiabatic Logic in Cadence Virtuoso. Semiconductor Memory Classification, Memory Timing: Definitions, Memory Architecture, Array-Structured Memory Architecture, Hierarchical Memory Architecture, 6T SRAM, 3-Transistor DRAM Cell, 1-Transistor DRAM Cell, Read-Only Memory, Programming the ROM, Programming the ROM, Fuse (PROM). EPROM, EEPROM, MOS OR ROM, MOS NOR ROM, MOS NAND ROM, Pre-charged MOS NOR ROM, Row Decoders, 4-to-1 tree-based column decoder, Flash Storage, […] Lecture 12B: Low Power VLSI Design Part-2: Architecture, Algorithmic, and RTL Level Optimization
33 mins
Architecture-Level Design – Parallelism, Pipelining, Retiming, Bus Segmentation, switching activity Reduction using gray code, FSM State Encoding, Bus Encoding for Reduced Power, RTL-Level Design – Datapath Reordering, RTL-Level Design – Memory Partition. Overview of Power Consumption, dynamic power dissipation, transition activity, Low-Power Gate-Level Design, Low-Power Architecture-Level Design, Algorithmic-Level Power Reduction, RTL Techniques for Optimizing Power, Gate-Level Design – Technology Mapping, Phase Assignment, Pin Swapping, Glitching Power, Static Glitch Example, Precomputation, Clock Gating, Input Gating, Reduced-Power Shift Register. The Binary Multiplication, The Array Multiplier, The Carry-Save Multiplier, Multiplier Floorplan, Transmission Gate XOR, Adder Cells in Array Multiplier, Sequential Multiplier, Booth Algorithm, Comparators, 0’s detector, 1’s detector, Equality comparator, Magnitude comparator, Shifters, The Binary Shifter, Multi-bit Shifters, The Barrel Shifter, Logarithmic Shifter, Shifter Using Mux. Semiconductor Memory Classification, Memory Timing: Definitions, Memory Architecture, Array-Structured Memory Architecture, Hierarchical Memory Architecture, 6T SRAM, 3-Transistor DRAM Cell, 1-Transistor DRAM Cell, Read-Only Memory, Programming the ROM, Programming the ROM, Fuse (PROM). EPROM, EEPROM, MOS OR ROM, MOS NOR ROM, MOS NAND ROM, Pre-charged MOS NOR ROM, Row Decoders, 4-to-1 tree-based column decoder, Programmable Logic […] Microprocessor Design, ALU Design, Half Adder, Full Adder, CMOS 28T Adder, CMOS 28T Mirror Adder, Ripple Carry Adder, Carry Look-Ahead Adder, Carry Bypass or Carry Skip Adder, Carry Ripple versus Carry Bypass, Manchester Carry Chain, Linear Carry-Select Adder, Square Root Carry-Select Adder, Adder Delays - Comparison, Serial Adder, 4 Bit-Adder Subtractor, Binary Coded Decimal Adder.