Lesson Archives
Negative Feedback, Advantages of Negative Feedback, Gain Desensitization, Bandwidth Extension, Noise Reduction, Basic Feedback Topologies, Series-Shunt Feedback Amplifier (Voltage-Voltage Feedback), Series-Series Feedback Amplifier (Current-Voltage Feedback, Shunt-Shunt Feedback Amplifier (Voltage-Current Feedback), Shunt-Series Feedback Amplifier (Current-Current Feedback), Analysis of Feedback Amplifiers, Solved Examples on Feedback. Problems and Solutions Feedback. CMOS Differential Logic, Cascode Voltage Switch Logic (CVSL), Dynamic CVSL, Dynamic CVSL with Charge Keepers, Differential current switch logic, Dynamic threshold voltage MOSFET (DTMOS), Dual Vt CMOS logic circuit, Gate Diffusion Input(GDI), BiCMOS, BiCMOS Inverter with base pull-down transistor, BiCMOS NAND, BiCMOS NOR, Full-Rail BiCMOS with Resistive Shunts, Full-Rail BiCMOS with Active Shunts, Full-Rail BiCMOS […] High Pass Filters, Low Pass Filters, Amplifier Transfer Function, High-Frequency Response, Open-Circuit Time Constant Method, Miller’s Theorem, High-Frequency Response of CS Amp, High-Frequency Response of CE Amp, Frequency Response of CG Amplifier, Frequency Response of Source Followers, Frequency Response of Cascode Amplifier, Frequency Response of Differential Amplifier NMOS Current Mirror, PMOS Current Mirror, Generating I REF, Influence of the Channel Modulation Parameter, Common centroid design evens out the effect of the process variation, Current Mirror Analysis, Standard Cascode Current Mirror, Triple Cascode Current Mirror, Low Voltage Cascode Current Source 1, Low Voltage Cascode Current Source 2, Wilson Current Mirror, Biasing Techniques, Simple […] Characteristics of DC Voltage Sources, NMOS, and PMOS voltage sources, CMOS CURRENT MIRRORS, Small Signal Equivalent Circuit Model, NMOS Current Mirror, PMOS Current Mirror, Generating I REF, Influence of the Channel Modulation Parameter λ, Common centroid design evens out the effect of the process variation, Current Mirror Specifications, Current Mirror Analysis, Eliminate the Systematic Error, […] MOS Differential Pair, Differential Gain, Common mode Gain, Common mode Range ICMR, Active Loads, MOS Differential Pair with MOS Loads, Differential pair with (a) diode-connected and (b) current-source loads, Problems with Current-Source MOS Loads, Differential Amplifier with a Current Mirror Load, Design of Differential Amplifier with a Current Mirror Load, Gilbert Cell. Basic MOS Differential Pair, The “Virtual Ground” Concept, The “Half-Circuit” Concept, Common-Mode Response, CS stage with Source Degeneration, Single-ended Common-Mode Response of a symmetric amplifier, Common-mode response in the presence of resistor mismatch, CM response with finite tail capacitance, Degenerated Differential Pairs, Degenerated differential pair with split tail current source. Timing Constraints of a Flip-flop, Setup Time Hold Time, Clock skew , Clock Jitter, Clock Uncertainty , Data setup violation caused by clock jitter, Data hold time violation caused by clock jitter, Setup (Max) Constraint, Setup Slack , Positive Slack , Negative Slack , Hold (Min) Constraint, Timing Constraints of a Sequential Circuit, Maximum Clock […] Examples of Pipelined Architectures, Pipelining with Latches, Clock-Skew Insensitive C2MOS Register, Pipelined Logic using C2MOS, NORA CMOS Noise Margin, Resistive Load Inverter, VTC Curve, Load line, Ratioed Logic, MOSFET Current Equations, Calculation of VOH, VIH, Noise Margin High NMH, Noise Margin Low NML, Enhancement-Load nMOS Inverter, Depletion-Load nMOS Inverter, The CMOS Inverter, Important properties of static CMOS, The PMOS Load Line, CMOS Inverter Load Characteristic, CMOS Inverter VTC, CMOS Inverter Switching Threshold, […]