Lesson Archives
SSI, MSI, LSI and VLSI, ENAIC - The First Electronic Computer, Evolution of Digital Technology, RTL, DTL, TTL, ECL, CMOS Logic Advantages and Disadvantages, Moore’s Law, ITRS Prediction of Power Consumption, Limitations of Static CMOS, Power Dissipation in CMOS Circuits, Static Loss, Short Circuit Loss, Switching Loss, Figure of Merits of a Digital Circuits, Noise […] 6T SRAM, Write and Read Operation. Sense Amplifer Design in LT SPICE using TSMC 180 nm CMOS devices. Pass Transistor Logic AND OR and Full Adder Design in LT SPICE using TSMC 180 nm CMOS devices. Limitations of Static CMOS design. Dynamic and Domino Full adder Design in LT SPICE using TSMC 180 nm CMOS devices. NAND, NOR and FULL Adder design in LT SPICE using TSMC 180 nm CMOS devices. Transitor Sizing in NAND, NOR and Full Adder. 2:1 Multiplexer, 2:1 MUX, 4:1 Multiplexer, 4:1 MUX, 4:1 MUX Using 2:1 MUX, Tri-State Buffer, 4:1 MUX using Tri-state buffers and 2 to 4 Decoder, Boolean Function implementation using Multiplexers 2 to 4 Line Decoder, 2 to 4 Line Decoder with Enable, 3 to 8 Line Decoder, Implementing a 3 to 8 decoder using two 2 to 4 decoders with enable pin, 4 to 16 decoder, Implementing function using Decoders, Encoder, Priority Encoder, Binary to Gray Using Encoder-Decoder Inverter-based VCO. CMOS Ring Oscillator. Measurement of Inverter Threshold Voltage, Static Power, Short-circuit Power, Switching Power and Propagation Delay of TSMC 180 nm CMOS inverter in LT SPICE