Digital Design Lab

Lab 9 : Combinational Circuit Design using Decoders and Multiplexers in Xilinx ISE

Verilog Conditional Statements, The Decoder, Odd Parity Generator using a Decoder. The Multiplexer, Multiplexer based Full Adder, Parity Generator with Mux, Full Adder with Decoder.

Lesson Intro Video

Lab 8 : Sequential Circuit Design using D and JK Flipflops in LT SPICE (Prev Lesson)
(Next Lesson) Lab 10 : Sequential Circuit Design using Flip-flops in Xilinx ISE
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