74138 Decoder, Implementation a Full Adder using 74138 Decoder, Implementation a Majority Circuit using 74138 Decoder, Implementation a Full Adder using 74151 Mux, Implementation a Majority Circuit using 74151 Mux.
Digital Design Lab
Home Digital Design Lab Lab 7 : Combinational Circuit Design using Decoders and Multiplexers in LTSPICE
Course Curriculum
- Lab 1 : Introduction to LT SPICE and Implementation of Majority Circuit53 mins
- Lab 2 : Parity Generator and Adders with LT Spice using 7400 Series TTL Gates25 mins
- Lab 3 : Four-Bit Parallel Adder & BCD Adder in LT SPICE16 mins
- Lab 4 : Introduction to Verilog and Implementation of Majority Circuit in Xilinx ISE22 mins
- Lab 5 : Dataflow Modelling and Implementation of Adders in Xilinx ISE35 mins
- Lab 6 : Dataflow Modelling Implementation of 4-Bit Adder & BCD Adder in Xilinx ISE25 mins
- Lab 7 : Combinational Circuit Design using Decoders and Multiplexers in LTSPICE10 mins
- Lab 8 : Sequential Circuit Design using D and JK Flipflops in LT SPICE12 mins
- Lab 9 : Combinational Circuit Design using Decoders and Multiplexers in Xilinx ISE13 mins
- Lab 10 : Sequential Circuit Design using Flip-flops in Xilinx ISE15 mins
- Lab11: Implementation of Majority Circuit using 74XX, TTL Gates in Tinkercad25 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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