Digital VLSI

Lessons

1. Low Power Techniques for Digital VLSI Circuits

   45 mins

   Sanjay Vidyadharan

2. 180 nm CMOS Inverter Characterization with LT SPICE

   16 mins

   Sanjay Vidyadharan

3. Importing CMOSS 60 nm, 45 nm, 22nm, 16nm, 10 nm, and 7nm Technology Files into LT SPICE

   10 mins

   Sanjay Vidyadharan

4. Importing Stanford University CNFET model into Cadence Virtuoso

   15 mins

   Sanjay Vidyadharan

5. Measurement of Power and Delay Analysis of CMOS digital Circuits in Cadence.

   56 mins

   Sanjay Vidyadharan

6. Importing PTM 7nm, 16 nm, 22nm CMOS Technology files Into Virtuoso Cadence®

   10 mins

   Sanjay Vidyadharan

7. TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder

   25 mins

   Sanjay Vidyadharan

8. TSMC 180 nm NMOS Characterization Transfer Characteristics & Output Characteristics in LT Spice

   10 mins

   Sanjay Vidyadharan

9. The Layout of NAND Gate in Cadence Virtuoso. DRC and LVS Check

   32 mins

   Sanjay Vidyadharan