Digital VLSI

Low Power Techniques for Digital VLSI Circuits

Motivation for  Low Power, ITRS Prediction of Power Consumption, Sources of  Power Dissipation, Static Loss, CMOS Static Power, Short Circuit Loss, Switching Loss, Dynamic Power, Static CMOS Logic, Dynamic Logic, Domino Logic, Pass Transistor Logic, Clock Gating. Multi Vdd Technique, Multi Vth Technique, Architectural & Algorithmic Optimization, Tunnel Field-Effect Transistors, CNFETs Adiabatic Logic,


Lesson Intro Video

(Next Lesson) 180 nm CMOS Inverter Characterization with LT SPICE
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