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Digital VLSI

Home Digital VLSI The Layout of NAND Gate in Cadence Virtuoso. DRC and LVS Check

The Layout of NAND Gate in Cadence Virtuoso. DRC and LVS Check

32 mins

Digital VLSI

Lesson Intro Video

TSMC 180 nm NMOS Characterization Transfer Characteristics & Output Characteristics in LT Spice (Prev Lesson)
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Course Curriculum

  • Low Power Techniques for Digital VLSI Circuits
    45 mins
  • 180 nm CMOS Inverter Characterization with LT SPICE
    16 mins
  • Importing CMOSS 60 nm, 45 nm, 22nm, 16nm, 10 nm, and 7nm Technology Files into LT SPICE
    10 mins
  • Importing Stanford University CNFET model into Cadence Virtuoso
    15 mins
  • Measurement of Power and Delay Analysis of CMOS digital Circuits in Cadence.
    56 mins
  • Importing PTM 7nm, 16 nm, 22nm CMOS Technology files Into Virtuoso Cadence®
    10 mins
  • TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder
    25 mins
  • TSMC 180 nm NMOS Characterization Transfer Characteristics & Output Characteristics in LT Spice
    10 mins
  • The Layout of NAND Gate in Cadence Virtuoso. DRC and LVS Check
    32 mins
Teacher
Sanjay Vidyadharan
Role : Professor
  • Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
  • Experience : 25 Years
  • Specialist in : Electronics and Electrical Engineering
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About Me

I was very fortunate to get an opportunity to serve the Indian Airforce for 22 years in various capacities starting as a Senior Technical Engineer in 1994 and retiring as Joint director (Helicopter Maintenance) in 2016. I opted for voluntary retirement from IAF to pursue my passion for academics. I am presently working at BITS-Pilani as Assistant Professor, sharing my experience with young budding engineers.

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