Lesson Archives
Single-Ended and Differential Operation, Single-Ended and Differential Operation, Transmission Line Noise Cancellation, Power Supply Noise Cancellation, Converting Single Input to Differential, Differential Amplifier Definitions, Simple Differential Circuit, Basic MOS Differential Pair, MOS Differential Pair with current source, Differential Transconductance Gain vs. Input Voltage, Maximum Differential Transconductance Gain Occurs at ΔVin=0, Differential Voltage Gain, Comparison: Differential […] CS Amplifier, Design Steps, CS stage with source degeneration, CS Amplifier Output Resistance, CS stage with source degeneration and bypass capacitor, CS Amp with Current Source Supply, P-Channel CS Amplifier, CS Amplifier with Active Load, Active Loads, Common Gate Amplifier, Common Drain Amplifier, Telescopic Cascode Amplifier, Cascode Amplifier Output Resistance, Cascode Amplifier with Simple Active […] MOSFET Large Signal Equivalent, MOSFET Small Signal Equivalent, Transconductance, Output Conductance, Backgate Transconductance, High-Frequency Model, CS Amplifier Design Steps, Load-Line Analysis to find Q, Miller Capacitance, Q-point Stability, CS Amplifier with source degeneration, CS Amplifier with source degeneration and bypass capacitor, CS Amp with Current Source Supply, P-Channel CS Amplifier, CS Amplifier with Active Load. […] A practical definition of the threshold voltage VT, inversion layer, depletion layer, work function difference, surface inversion, body effect, Derivation of MOSFET Current Equation, MOSFET Current in Linear and Saturation regions, MOSFET as Switch, NMOS can pass perfect 0 but not 1, PMOS pass perfect 1 but not 0, MOSFET Body connection, LATCH in MOSFET. Pipeline Concept, Sequential execution, Pipelined execution, Why RISC is better for Pipeling, Review - Single-Cycle Processor, Basic Pipelined Processor, Role of Cache Memory, Pipeline Performance, Pipeline Hazard, Data hazard, Instruction (control) hazard and Structural hazard, Operand Forwarding, Handling data hazards in Software, Instruction Queue, and Prefetching, Branch Prediction, Dynamic Branch Prediction, Addressing Modes Instruction Set Example, Instruction Timing State, Instruction Execution with No Overlap, Instruction Execution with Overlap, Timing Signals, Ring Counter, Counter with Decoder, Johnson Counter, Four-Phase Clocks, Two-level control store (organization), Exceptions, Interrupts, internal interrupts, external interrupts, Immediate Interrupt, Deferred Interrupt MIN execution unit block diagram, MIN execution unit block diagram, Execution Sequences for Register-to-Register, implementation of PC control, T2 Control, Register Control, Control Word Format, ALU Control, State Sequencer. Verilog Code for D Latch, D Flip-flop and D Flip-flop with Reset and Verilog Code for D Flip-flop test. State Identifiers, Register to Register Operations, Execution Sequences with a Memory Operand Reference, Branch Instruction, Examples Store Magnitude of a number, Sorting a number. Technology Scaling, constant field scaling, constant voltage scaling, Interconnects scaling.