Lesson Archives
NMOS Current Mirror, PMOS Current Mirror, Generating I REF, Influence of the Channel Modulation Parameter, Common centroid design evens out the effect of the process variation, Current Mirror Analysis, Standard Cascode Current Mirror, Triple Cascode Current Mirror, Low Voltage Cascode Current Source 1, Low Voltage Cascode Current Source 2, Wilson Current Mirror, Biasing Techniques, Simple […] Characteristics of DC Voltage Sources, NMOS, and PMOS voltage sources, CMOS CURRENT MIRRORS, Small Signal Equivalent Circuit Model, NMOS Current Mirror, PMOS Current Mirror, Generating I REF, Influence of the Channel Modulation Parameter λ, Common centroid design evens out the effect of the process variation, Current Mirror Specifications, Current Mirror Analysis, Eliminate the Systematic Error, […] MOS Differential Pair, Differential Gain, Common mode Gain, Common mode Range ICMR, Active Loads, MOS Differential Pair with MOS Loads, Differential pair with (a) diode-connected and (b) current-source loads, Problems with Current-Source MOS Loads, Differential Amplifier with a Current Mirror Load, Design of Differential Amplifier with a Current Mirror Load, Gilbert Cell. Basic MOS Differential Pair, The “Virtual Ground” Concept, The “Half-Circuit” Concept, Common-Mode Response, CS stage with Source Degeneration, Single-ended Common-Mode Response of a symmetric amplifier, Common-mode response in the presence of resistor mismatch, CM response with finite tail capacitance, Degenerated Differential Pairs, Degenerated differential pair with split tail current source. Timing Constraints of a Flip-flop, Setup Time Hold Time, Clock skew , Clock Jitter, Clock Uncertainty , Data setup violation caused by clock jitter, Data hold time violation caused by clock jitter, Setup (Max) Constraint, Setup Slack , Positive Slack , Negative Slack , Hold (Min) Constraint, Timing Constraints of a Sequential Circuit, Maximum Clock […] Examples of Pipelined Architectures, Pipelining with Latches, Clock-Skew Insensitive C2MOS Register, Pipelined Logic using C2MOS, NORA CMOS Noise Margin, Resistive Load Inverter, VTC Curve, Load line, Ratioed Logic, MOSFET Current Equations, Calculation of VOH, VIH, Noise Margin High NMH, Noise Margin Low NML, Enhancement-Load nMOS Inverter, Depletion-Load nMOS Inverter, The CMOS Inverter, Important properties of static CMOS, The PMOS Load Line, CMOS Inverter Load Characteristic, CMOS Inverter VTC, CMOS Inverter Switching Threshold, […] Single-Ended and Differential Operation, Single-Ended and Differential Operation, Transmission Line Noise Cancellation, Power Supply Noise Cancellation, Converting Single Input to Differential, Differential Amplifier Definitions, Simple Differential Circuit, Basic MOS Differential Pair, MOS Differential Pair with current source, Differential Transconductance Gain vs. Input Voltage, Maximum Differential Transconductance Gain Occurs at ΔVin=0, Differential Voltage Gain, Comparison: Differential […] CS Amplifier, Design Steps, CS stage with source degeneration, CS Amplifier Output Resistance, CS stage with source degeneration and bypass capacitor, CS Amp with Current Source Supply, P-Channel CS Amplifier, CS Amplifier with Active Load, Active Loads, Common Gate Amplifier, Common Drain Amplifier, Telescopic Cascode Amplifier, Cascode Amplifier Output Resistance, Cascode Amplifier with Simple Active […] MOSFET Large Signal Equivalent, MOSFET Small Signal Equivalent, Transconductance, Output Conductance, Backgate Transconductance, High-Frequency Model, CS Amplifier Design Steps, Load-Line Analysis to find Q, Miller Capacitance, Q-point Stability, CS Amplifier with source degeneration, CS Amplifier with source degeneration and bypass capacitor, CS Amp with Current Source Supply, P-Channel CS Amplifier, CS Amplifier with Active Load. […]