Lesson Archives
Amplitude Modulation, Need for Modulation, AM modulator demodulator, Equation of AM Signal , Modulation Index, Power and Bandwidth of AM Signal Envelope/Diode AM Detector Synchronous or Coherent Demodulation Diode vs. Coherent Double Sideband Suppressed Carrier DSBSC Modulator Costas Loop Single Sideband Suppressed Carrier SSBSC Modulator SSBSC Demodulator DC Motors: Motor Characteristics, Two Point Starter, Three point Starter, DC Shunt wound Motors, DC Series Wound Motors , Separately Excited DC motors, Speed regulation. DC Generators, Simple Loop generator, Split Ring, Commutator, Multi-pole, Yoke, Armature, Lap and wave winding, EMF equation, Shunt , series and Compound DC generators, Separately excited, Voltage regulation, Characteristics curves, applications of DC generators. Flip-flop code in Verilog. Test bench for Sequential Circuits, D Flip-flop with Reset, Testbench for D Flip-flop with Reset Verilog Conditional Statements, The Decoder, Odd Parity Generator using a Decoder. The Multiplexer, Multiplexer based Full Adder, Parity Generator with Mux, Full Adder with Decoder. The 7474 D Flipflop, Design a Counter using D-Flipflop, 74107 JK Flipflop, Design a Gray Counter using JK-Flipflop 74138 Decoder, Implementation a Full Adder using 74138 Decoder, Implementation a Majority Circuit using 74138 Decoder, Implementation a Full Adder using 74151 Mux, Implementation a Majority Circuit using 74151 Mux. Handling multi-bit data, Concatenation to group data, 4-bit Adder, 4-Bit Adder Subtractor Dataflow Modelling, Initialization, VLSI Design Levels, Gate Level Design, Dataflow Design, Half Adder with dataflow modeling, Full Adder using Half Adder with Gate level modeling, 4-bit Parallel Adder Gate Level Modelling, Verilog Code, Three-bit Majority Circuit, Parity Encoder, Gray to Binary code.