Lesson Archives
ADC (Analog-to-Digital Converter), Interface with 8086, SOC Start of Conversion, EOC End of Conversion, ADC 0808 / 0809, Block Diagram, Pin Diagram, Successive Approximation ADC, Timing Diagram, ADC 0804, DAC0830 Block Diagram, Pin Diagram, Successive Approximation ADC, Timing Diagram, ADC 0804, DAC0830, R-2R Ladder, R-2R Ladder DAC Input & Output Interface, Interface with 8259A, PIN Diagram 8259, B8259A Block Diagram, Cascaded 8259A, Addressing 8259A, INITIALIZATION COMMAND WORDS (ICWS) ICW 1, ICW 2, ICW 3, & IC4 , Operation Command Words (OCWs), OCW 1, OCW 2 & ICW 3 Programming 8259. WAP 8259 Solved Examples 8259 Pin diagram of 8253/8254, Control word Format, Programming the Counters, Reading the Counters, Read-Back Command, Counter Latch, Modes of Operation, Mode 0 –Interrupt on Terminal count, Mode 1 Hardware re-triggerable one-shot, Mode 2 Rate Generator (Divide by N counter) Mode 3 Square Wave Generator, Mode 4 Software triggered strobe, Mode 5 Hardware triggered strobe, Reading […] Features of 8253/8254, Pin diagram of 8253/8254, Memory mapping, Control word Format, Programming the Counters, Reading the Counters, Read-Back Command, Counter Latch, Modes of Operation, Modes of counting, Mode 0 –Interrupt on Terminal count, Mode 1 Hardware re-triggerable one-shot Modes of operation of 8255, Examples, Handshaking signal, Input Read, Output Write, MODE 1 (Strobed I/O mode), MODE 2 (Strobed Bidirectional I/O mode), BIT Set Reset (BSR) mode, Display Interfacing 8255- PPI, Pin Diagram of 8255, Selection of ports, Internal block diagram of 8255, Interfacing with 8086, Control word Format, Examples, Modes of operation of 8255, Mode 0, Mode 1 and Mode 2 Operation, Control word Format, Examples IO-Mapped & Memory-Mapped , Modes of I/O Instructions, Isolated I/O Direct I/O Indirect I/O String IN and OUT, I/O Design in 8086, Switch Interface LED Interface, Simple Output Port using 74373 Latch , Simple Input Port using 74245 Trans-receive Tristate Buffer, Key Debouncing Circuits Odd and Even Memory banks, 2716 ROM, 6116 SRAM, Interface 4K of ROM to 80286, Chip Selection with BHE and A0, Byte and Word selection on 8086 8086 Bus Cycle, Machine Cycle, Instruction Cycle, T States Memory Write Operation, Memory Read Operation, IO Write Operation, IO Read Operation, Fetch Cycle Opcode Fetch Memory access time TCLRL- Time from Clock to Read Line, TDVCL – Time Data Valid to Clock, TCLAV and Loop Delay Calculations 8088 Memory Interfacing, Example: f Interfacing 8 K Bytes of memory to 8088 using 2K memory chips, Memory Address decoding, Absolute Addressing, Incremental Addressing, Memory maps