Lesson Archives
Binary Ripple Counter, 4-bit Binary Ripple Up-Counter, 4-bit Binary Ripple Down-Counter, BCD Ripple Counter, BCD Ripple Counter with JK FFs, Multi-digit BCD Counter. Binary Synchronous Counter, 3 bit binary counter, 4-bit Binary Synchronous Counter, Up-Down Binary Counter, Synchronous BCD Counter, Binary Counter with Parallel Load, Ring Counter, Johnson Counter, the Unused States in Counters. Pipelining, Latch Based Clocking, Slack Transfer, Self-Timed Circuit Design, Completion-Signal Generation, Dual-Rail Coding, Manchester-Carry Adder Circuit, Self-Timed Adder Circuit, Replica Delay, Completion-Signal Generation using Current Sensing, Self-Timed Signaling, two-phase hand-shaking, Muller C-element, Two-Phase Self-Timed FIFO, four-phase hand-shaking, Four-Phase Self-Timed FIFO. Logical Effort, Delay in a Logic Gates, effective fanout, Intrinsic Delay , Electrical effort, Parasitic Delay, Path effective fanout, Path Logical Effort, Path Effort H = FG, Branching Effort, Logical Effort Example, Best Stage Effort, Delay of a fanout-of-4 (FO4) inverter,Stage Delay Static CMOS, Body-Effect, DIBL, Static Two-Input NAND Gate, Transistor Sizing for a Complex Gate, Shortest Path First Sizing, Worst Path First Sizing, Chain Network Elmore Delay, Fanin considerations, Propagation Delay as a function of fanin, Progressive sizing, Input re-ordering, Logic Restructuring, Isolating fan-in from fan-out using buffer insertion. Hardware Description Language vs Software, Gate Level Modelling in Verilog VLSI System Specifications, Technical Requirements, Market requirements, and Economic Considerations, Technical Requirements include Size of the IC, the maximum amount of power that can be consumed and the performance and the functionality, VLSI Design Styles, FPGA, Standard Cell or Semi-Custom Design, Full-Custom Design, VLSI Design Flow, Low Power VLSI Architecture, VLSI Architecture Example, Function Delay, […] Serial Transfer, Parallel Transfer, Parallel Load 4 Bit Register, Shift Register, Data Encryption, Pseudo-Random Series. Design of Clocked Sequential Circuits, State Table Reduction, Solved Examples, Solved Problems and Solutions on State Table Reduction & Implication Chart Reduction. Clock Distribution, Network Types: H-Tree Model, CAD for Tree Architecture, Grid/Mesh Clock Distribution, Hybrid Architecture: Tree + Cross-links, Hybrid Architecture: Mesh + Trees, Clock Gating