Lecture 21: Registers 42 mins Digital Design Serial Transfer, Parallel Transfer, Parallel Load 4 Bit Register, Shift Register, Data Encryption, Pseudo-Random Series Lecture_21_-RegistersDownload Lesson Intro Video Lecture 20: State Table Reduction (Prev Lesson) (Next Lesson) Lecture 22: Asynchronous Counters Back to Digital Design No Comments Give a comment Cancel reply Save my name, email, and website in this browser for the next time I comment.
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