Combinational vs. Sequential Circuits, Half Adder, Time Delay for the Half Adder, NAND vs. XOR, Full Adder, Output delay, Full-adder implemented with two half adders and one OR gate, Ripple Carry Adder, Carry Look-Ahead Adder, 4 Bit-Adder Subtractor, BCD ADDER.
Digital Design 2021
Course Curriculum
- Lecture 0: Introduction to Digital Design Course9 mins
- Lecture 1: Introduction to Digital Systems40 mins
- Lecture 2: Number System Part 128 mins
- Lecture 3: Number System Part 254 mins
- Lecture 4: Binary Codes37 mins
- Lecture 5: Boolean Algebra: Part 142 mins
- Lecture 6: Boolean Algebra: Part 228 mins
- Lecture 7: K-Maps Part 153 mins
- Lecture 8: K-Maps Part 224 mins
- Lecture 9: Five Variable K-Maps24 mins
- Lecture 10: Quine-McCluskey (QM) Technique49 mins
- Lecture 11: Logic Gate Realization56 mins
- Lecture 12: Hazards in Digital Circuits13 mins
- Lecture 13: Combinational Logic and Arithmetic Circuits55 mins
- Lecture 14: Multipliers and Magnitude Comparators25 mins
- Lecture 15: Decoders and Encoders45 mins
- Lecture 16: Multiplexers and De-multiplexers28 mins
- Lecture 17: Sequential Logic, SR, D Latch35 mins
- Lecture 18: Sequential Logic Flipflops37 mins
- Lecture 19: Sequential Circuit Design38 mins
- Lecture 20: Sequence Detector17 mins
- Lecture 21: State Table Reduction & Implication Chart36 mins
- Lecture 22: Registers27 mins
- Lecture 23: Synchronous Counters40 mins
- Lecture 24: Asynchronous Counters17 mins
- Lecture 25: Applications of Sequential Circuits27 mins
- Lecture 26: ADC and DAC43 mins
- Lecture 27: Memory32 mins
- Lecture 28: Programmable Logic Devices24 mins
- Lecture 29: Digital Logic Families44 mins
- Lecture 30: Demonstration of RTL, DTL, CMOS NAND, and NOR in LT SPICE13 mins
Teacher
Sanjay Vidyadharan
Role : Professor
- Website : https://universe.bits-pilani.ac.in/pilani/vidhyadharan/Profile
- Experience : 25 Years
- Specialist in : Electronics and Electrical Engineering
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