Lesson Archives
Current Mirrors, Current mirror biasing using a resistor, Supply-Independent Biasing, Addition of RS to define the currents, start-up device , Temperature-Independent References, Negative-TC Voltage, Positive-TC Voltage, Band gap Reference , Realization of a pnp bipolar transistor in CMOS technology , Realization of a pnp bipolar transistor in CMOS technology , Constant-Gm Biasing. Error Detection,Physical Redundancy, Dual Modular redundancy (DMR) with a comparator, Triple modular redundancy (TMR), Temporal Redundancy, Information Redundancy, Hamming Code, Odd or Even Parity Check, Information Redundancy, Error Detection in Microprocessor Cores, arithmetic codes, Re-execution with Shifted Operands (RESO) : Adder, Multipliers Tightly Lockstepped Redundant Cores, Redundant Multithreading Without Lockstepping, Dynamic Verifcation of Invariants, Control […] Analog Testing Difficulties, Modeling Problems, Simulation Error, Tester Measurement Error, For mixed-signal chips, Test Accessibility Problems, Information Flow, Catastrophic or Hard faults, Parametric or soft faults, Analog Fault Models, multiple parametric faults, Levels of Abstraction, Types of Analog Testing, 1. Specifications based Testing, 2. Structural fault-model based Testing, DC fault simulation of non-linear circuits, AC […] BIST Hierarchy, BIST Implementation, BIST Pattern Generation, ROM, Linear feedback shift register (LFSR), Binary Counters, Modified Counters, LFSR and ROM, Cellular Automaton, BIST Pattern Generation, Exhaustive Pattern Generation, Hardware partitioning, Sensitized path segmentation, Pseudo-Exhaustive Pattern Generation, Random-pattern testing and fault coverages, Linear-feedback shift-register (LFSR), Pseudo-Random Pattern Generation, BIST Response Compaction, Compaction, Compression, Signature, Single Bit […] Design for Testability, Observability & Controllability, Ad Hoc Design for Testability, Method of Test Points, Improving controllability, Multiplexing monitor points, demultiplexer for control points, scan design, A single-clock scan flip-flop, A two-clock scan flip-flop, Scan Design Rules, Scan test length, Overheads of Scan Design, Gate overhead, Area overhead, Performance overhead, Design Automation, full-scan design, Partial-Scan […] Delay Fault, Path-Delay Test, Path-delay fault, Non-robust path-delay test, Robust path-delay test, Delay Algebra, Five-valued algebra for path-delay tests, Test Generation for Combinational Circuits, Transition Faults, Delay Test Methodologies, Slow-Clock Combinational Test, Enhanced-Scan Test, Normal-Scan Sequential Test, Variable-Clock /Slow Clock Non-Scan Sequential Test, Rated-Clock Non-Scan Sequential Test. Types of Memories, 1. Dynamic Random Access Memory (DRAM), 2. Static Random Access Memory (SRAM), 3. Cache DRAM (CDRAM), 4.Read-Only Memories (ROMs/EPROMs/EEPROMs), Memory Organization, Memory Testing, Static faults, Dynamic Faults, Fault Models, Stuck-at faults,Transition faults,Coupling faults, Neighborhood pattern sensitive fault, Address decoder fault, March Test Notation, Inversion Coupling Faults, Idempotent Coupling Faults, Dynamic Coupling Faults,Bridging […] ATPG for Single-Clock Synchronous Circuits, Time-Frame Expansion Method, Assumptions, Single Synchronized Clock for all FFs, Single Stuck-at Faults in Next Stage and Output Stage Blocks, No faults internal to FFs, No Faults in Clock Path, Time-Frame Expansion with D Algorithm, Sequential Depth of FF, Solved examples, Time-Frame Expansion with 9-Valued Algorithm, Time-Frame Expansion with Muth […] ATPG Algorithm, Roth’s D-Algorithm (D-ALG), Goel’s PODEM algorithm, Fujiwara and Shimono’s FAN algorithm, Prime Implicants, D-Calculus and D-Algorithm (Roth), singular cover, D-frontier, Unique D-frontier, J-frontier, Primitive D-cubes of failure (PDCF), Forward implication, Backward implication, D-Drive , Advantages and disadvantages of D-Calculus and D-Algorithm (Roth)