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  • Sanjay Vidhyadharan on TSMC 180 nm CMOS Full Adder in LT Spice, Measurement of Delay and Power, Sizing of Transistors of 28-T CMOS Full Adder
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Dept. of EEE,
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I was very fortunate to get an opportunity to serve the Indian Airforce for 22 years in various capacities starting as a Senior Technical Engineer in 1994 and retiring as Joint director (Helicopter Maintenance) in 2016. I opted for voluntary retirement from IAF to pursue my passion for academics. I am presently working at BITS-Pilani as Assistant Professor, sharing my experience with young budding engineers.

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